#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3

#**************************************************************
# Create Clocks (Base clock and JTAG)
#**************************************************************
create_clock -name base_clk -period 20.000 -waveform {0.000 10.000} CLK0
create_clock -name jtag_clk -period 100.000 [get_ports {altera_reserved_tck}] -add

#create_clock -period 50 -name nFCS [get_ports {nFCS}]

#create_generated_clock -name clk -source {pll_instance|altpll_component|pll|inclk[0]} -divide_by 3 -multiply_by 8 -duty_cycle 50.00 {pll_instance|altpll_component|pll|clk[0]}
#create_generated_clock -name ctl_clk -source {pll_instance|altpll_component|pll|inclk[0]} -divide_by 3 -multiply_by 4 -duty_cycle 50.00 {pll_instance|altpll_component|pll|clk[1]}
#create_generated_clock -name sdram_clk -source {pll_instance|altpll_component|pll|inclk[0]} -divide_by 3 -multiply_by 4 -phase -180.00 -duty_cycle 50.00 {pll_instance|altpll_component|pll|clk[2]}


derive_pll_clocks

set sdram_clk pll_instance|altpll_component|pll|clk[2]

create_generated_clock -name ram_clk_pin -source $sdram_clk -offset 0.2 [get_ports {CLK}]


#set_clock_groups -asynchronous -group {altera_reserved_tck}
#set_clock_groups -asynchronous -group {nFCS}
#set_clock_groups -asynchronous -group {clk}
#set_clock_groups -asynchronous -group {ctl_clk sdram_clk}

set_clock_groups -exclusive -group {jtag_clk altera_reserved_tck} -group {base_clk} \
-group [get_clocks {pll_instance|altpll_component|pll|clk*}]



#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************

derive_clock_uncertainty


set_false_path -from sld*
set_false_path -to sld*
set_false_path -from sdram_rw*

# skip LEDs
set_false_path -to leds*


set_multicycle_path -from DQ* -to *dat_o_r* -setup -end 3
set_multicycle_path -from DQ* -to *dat_o_r* -hold -end 2


#**************************************************************
# PCB & SDRAM parameters
#**************************************************************
# PCB delay
# 0.13 .. 0.21 ns per inch
#
# for z3sdram v1.2 min DQ length = 21mm, max DQ length = 42mm
#
#set tPCB_min 0.3
#set tPCB_max 0.5
set tPCB_min 0.08
set tPCB_max 0.34

# Data out hold time
set tOH_min 3.0
# Access time (CL = 2)
set tAC_max 6.0
# Address hold and setup
set tAH_min 0.8
set tAS_min 1.5
# Control hold and setup
set tCH_min 0.8
set tCS_min 1.5
# Data hold and setup
set tDH_min 0.8
set tDS_min 1.5


#**************************************************************
# Set Input Delay
#**************************************************************
# SDRAM data bus
set_input_delay -clock ram_clk_pin -max [expr $tAC_max + $tPCB_max] \
[get_ports {DQ[*]}]
set_input_delay -clock ram_clk_pin -min [expr $tOH_min + $tPCB_min] \
[get_ports {DQ[*]}]

# Zorro
#set tAFS_min 15
#set tHAF_min 10

# AD[31:8]
#set_input_delay -clock nFCS -max tAFS_min [get_ports (AD*)]
#set_input_delay -clock nFCS -min tHAF_min [get_ports (AD*)]


#**************************************************************
# Set Output Delay
#**************************************************************
# SDRAM address bus
set_output_delay -clock ram_clk_pin -max [expr $tAS_min + $tPCB_max] \
[get_ports {SA[*] BA[*]}]
set_output_delay -clock ram_clk_pin -min [expr 1.0 - $tAH_min - $tPCB_min] \
[get_ports {SA[*] BA[*]}]
# SDRAM control signals
set_output_delay -clock ram_clk_pin -max [expr $tCS_min + $tPCB_max] \
[get_ports {nCS0 nRAS nCAS nWE DQMH DQML}]
set_output_delay -clock ram_clk_pin -min [expr 1.0 - $tCH_min - $tPCB_min] \
[get_ports {nCS0 nRAS nCAS nWE DQMH DQML}]
# SDRAM data bus
set_output_delay -clock ram_clk_pin -max [expr $tDS_min + $tPCB_max] \
[get_ports {DQ[*]}]
set_output_delay -clock ram_clk_pin -min [expr 1.0 - $tDH_min - $tPCB_min] \
[get_ports {DQ[*]}]
